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cd34021-a.fm 15/01/98 1 VV6300 sensor integrated cmos colour image sensor with on-chip adc. key features general description VV6300 is a highly-integrated cmos image sensing device. in addition to a 160 x 120 pixel image sensor array, the device includes on-chip circuitry to drive and sense the array. the output stage of the sensor contains a successive approximation circuit which performs analogue-to- digital conversion of the photodiode array to produce 8-bit or 4-bit pixel data. the primary image size is 160 x 120 but border pix- els/lines can be enabled to give an effective image size of 164 x 124. VV6300 features electronic exposure and gain con- trol over a wide range, enabling the use of a single fixed-aperture lens. a bi-directional 2-wire serial communications inter- face allows the device to be configured and its oper- ating status monitored. the status information may also be multiplexed onto the digital output bus. nb . a colour processor will be required to convert the raw colourised pixel data into colour image information. ? standard image format: 160 x 120 ? 164 x 124 bayer patern colour pixel array ? variable frame rate (< 0.3 f/s - 60 f/s) ? on-chip 8-bit a/d convertor ? 8-bit and 4-bit conversion modes ? 8-wire and 4-wire parallel data output modes ? reduced flicker operation with 50hz and 60hz mains frequencies ? 2 serial data output modes ? automatic exposure and gain controller ? automatic black level calibration ? options selectable via serial interface ? configuration autoload from e 2 prom ? evaluation kit available (see seperate datasheet) block diagram sample & hold horizontal shift register photo diode array analog voltage refs. digital control logic sda scl vbltw vrt vcm vref2v5 vertical shift register clki clko clock circuit image format pixel resolution 160 x 120 pixel size 12 m m x 12 m m array size 1.92mm x 1.44mm power supply 5v +/-10% min.illumination 5 lux power 175 mw (typ.) s/n 36 db (typ.) exposure control automatic (25000:1) temperature -20 o c to +70 o c package ceramic 48lcc a/d convertor vped vcds d[7:0] sin fst qck vbg
cd34021-a.fm 15/01/98 2 VV6300 sensor main features bayer pattern colour array with default image format of 160 x 120. extra border pixel/lines can be enabled to give an image size of 164 x 124. shuffled read out to reduce pixel crosstalk. digital pixel data coding assigns 10 h as black and f0 h as white. other codes specify line sync and frame sync periods. on-chip 8-bit successive approximation analogue-to-digital convertor with 8-wire, 4-wire parallel and two serial data output modes. the VV6300 frame rates can be integer multiples of the mains supply frequencies used worldwide, i.e. 50hz and 60hz. this ensures reduced flicker operation of the sensor all VV6300 operating modes and system status information can be accessed via a two wire bidirectional serial interface. VV6300 features an automatic electronic exposure algorithm that enables the use of a single fixed-aperture lens. automatic gain control enhances operation under low light conditions. automatic black level control ensures consistent picture quality across the whole range of operating conditions. extensive use of automated operation and on chip references means that only a small number of passive components are needed to realise a complete video camera. on-chip voltage references simplifies the support circuitry and maintains device stability over a wide range of operating conditions. exposure control with automatic exposure control selected VV6300 uses a complex algorithm to automatically set the exposure value for the current scene. when combined with clock control and gain control the VV6300 can operate over a very wide range of illumination levels. where direct control of the exposure is required the exposure value can be directly selected by writing to the appropriate registers via the serial interface. clock control the system clock can be divided down internally to extend the operating range of VV6300 by allowing longer exposure times. the clock divisor can be varied from 1 to 8 in times two steps i.e there are 4 different values. note: changing the system clock divisor modifies the pixel and frame rate. gain control if the image is to dark and the exposure is already close to its maximum, VV6300 will increase the system gain. gain can be varied from x1 to x8 in times two steps i.e there are 4 different gain settings. if the scene is too dark and integration period has almost reached its maximum value the gain value is incremented by one step (i.e. doubled). if the gain setting changes the exposure value is automatically set to half the maximum integration period. the exposure controller then increases the exposure value as necessary. similarly if the image is too bright and the integration period is short then gain will be reduced by one step (i.e. divide by two). as before, the exposure value is set to half the maximum integration period. the exposure controller can then adjust the exposure value as necessary to provide a correctly exposed image.
cd34021-a.fm 15/01/98 3 VV6300 sensor package details device pinout 0.51 1.56 2.16 pin 1 1.016 pitch 14.22+/-2% viewed from below 0.53 0.55 glass lid base viewed from side die 0.86 0.5 13.7 the optical array is centred within the package to a tolerance of 0.2 mm, and rotated no more than 0.5 o tolerances on package dimensions 10% unless otherwise stated. glass lid placement is controlled so that no package overhang exists. all dimensions in millimetres 123456 43 44 45 46 47 48 18 nc 17 qck 16 fst 15 sin 14 vdd 13 dvdd 12 11 10 9 8 7 24 23 22 21 20 19 30 29 28 27 26 25 31 32 33 34 35 36 37 38 39 40 41 42 vrt vcds test hpix nc avss nc nc nc avdd nc nc vdd vss d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] vss vdd clki clko sda scl vss dvss autoloadb ce nc vreg nc nc nc vbloom vbltw vbg vref2v7 nc VV6300 viewed from above
cd34021-a.fm 15/01/98 4 VV6300 sensor pin function list oa - analogue output a - analogue input od - digital output d - digital input bi - bidirectional id - - digital input with internal pull-up od - digital output with internal pull-down pin name type description power supplies 6 avss gnd analogue ground 9 avdd pwr analogue power 13 dvdd pwr digital power 14 vdd pwr power 19 vdd pwr power 20 vss gnd ground 29 vss gnd ground 30 vdd pwr power 35 vss gnd ground 36 dvss gnd ground analogue outputs 1 vrt ia pixel reset voltage 2 vcds ia voltage reference 3 test ia analogue test 40 vreg ia reference voltage input 44 vbloom oa internal reference voltage 45 vbltw ia bitline test white reference 46 vbg oa internally generated bangap reference voltage 1.22v 47 vref2v5 oa internally generated reference voltage 2.5v digital outputs 16 fst od frame start. synchronises external image capture. 17 qck od pixel sample clock. qualifies video output for external image capture. 25-28 d[3:0] bi parallel 4-bit databus. d[0] serial data bus. 21-24 d[7:4] od parallel 4-bit databus. digital control signals 34 scl bi - serial bus clock (bidirectional, open drain) 33 sda bi - serial bus data (bidirectional, open drain) 37 autolo adb id enable autoload from eeprom 38 ce id - chip enable 4hpix id hold pixel value. 15 sin id frame timing reset(soft reset) system clocks 31 clki id oscillator input. 32 clko od oscillator output.
cd34021-a.fm 15/01/98 5 VV6300 sensor specifications spectral response absolute maximum ratings note: stresses exceeding the absolute maximum ratings may induce failure. exposure to absolute maximum ratings for extended periods may reduce reliability. functionality at or above these conditions is not implied. parameter value supply voltage -0.5 to +7.0 volts voltage on other input pins -0.5 to v dd + 0.5 volts temperature under bias -15 o c to 85 o c storage temperature -30 o c to 125 o c maximum dc ttl output current magnitude 10ma (per o/p, one at a time, 1sec. duration) 400 500 600 700 red green blue 1.0 0.8 0.6 0.4 0.2 0 with ir filter sensor response wavelength, nm 350 450 550 650 colourisation filter responses normalised response
cd34021-a.fm 15/01/98 6 VV6300 sensor dc operating conditions ac operating conditions 1. pixel clock = ckin / 2 2. serial interface clock must be generated by host processor. electrical characteristics 1. digital and analogue outputs unloaded - add output current. symbol parameter min. typ. max. units notes v dd operating supply voltage 4.75 5.0 5.25 volts v ih input voltage logic 1 2.4 v dd +0.5 volts v il input voltage logic 0 -0.5 0.8 volts t a ambient operating temperature -20 70 o c still air symbol parameter min. typ. max. units notes ckin crystal frequency 14.318 mhz 1 scl serial data clock 100 khz 2 symbol parameter min. typ. max. units notes i dcc digital supply current 10 ma 1 i add analog supply current 25 ma 1 i dd overall supply current 35 ma 1 v ref2v7 internal voltage reference 2.700 volts v bg internal bandgap reference 1.22 volts v oh output voltage logic 1 2.4 volts i oh = 2ma v ol output voltage logic 0 0.6 volts i ol = -2ma i ilk input leakage current -1 m a v ih on input 1 m a v il on input typical conditions, v dd = 5.0 v, t a = 27 o c
cd34021-a.fm 15/01/98 7 VV6300 sensor operating characteristics note: devices are normally not 100% tested for the above characterisation parameters, other than dark current signal (see blemish specification below). all voltage (v a , v ave , v sat , v xx% ) measurements are referenced to the black level, v black , and spot blemishes are excluded (see blemish specification below). v xx% refers to the output that is xx% of saturation, that is peak white t est conditions parameter min. typ. max. units note dark current signal 50 mv/sec modal pixel voltage due to photodiode leak- age under zero illumination with gain=1 (v dark = (v t1 - v t2 )/(t1-t2), calculated over two different frames sensitivity 6 v/luxsec v ave /lux10ms, where lux gives 50% satu- ration with gain=1 and exposure=10ms min. illumination 10 lux shading tba % variance of v ave over eight equal blocks at 66% saturation level illumination random noise -36 db rms variance of all pixels, at 66% satura- tion, over four frames smear tba % ratio of v ave of the area outside a rectangle 25 lines high illuminated at 500xv 50% level to v ave of the rectangle flicker tba % variation of v ave of one line from field to field at 66% saturation level illumination lag tba % average residual signal with no illumination in the field following one field of 66% sat. illumination blooming tba ratio of spot illumination level that produces 0.1xv sat output from immediately around the spot to the v sat spot illumination level (pin- hole target) the sensor is tested using the example support circuit illustrated later in this document. standard imaging conditions used for optical tests employ a tungsten halogen lamp to uniformly illuminate the sensor (to better than 0.5%), or to illuminate specific areas. a neutral density filter is used to control the level of illumination where required. illumination colour temp. 3200 o k clock frequency 14.318mhz exposure maximum gain x1 auto. gain control (agc) off
cd34021-a.fm 15/01/98 8 VV6300 sensor blemish specification a blemish is an area of pixels that produces output significantly different from its surrounding pixels for the same illumination level. the definition of a blemish pixel varies according to testing condi- tions as follows: note: gain is set to minimum and correction set to linear for all tests; measurement of blemishes for test 3 is conducted under standard illumination (see above), set to produce average output of 66% saturation level. the blemish specification is then defined as follows: nb, pixel blemishes may occur anywhere on the array. test exposure illumination blemish pixel output definition 1 - black frame minimum black differing more than 100 mv. from modal value. 2 - dark current maximum black output more than three times the modal value (see dark current signal above). 3 - pixel variation mid range 66% sat. differing more than 35mv from modal value. note: the mode of pixel values must be within 70 mv of 66% of v sat for all devices. max. no. of blemishes notes 4 unconnected single pixels 1 of up to four connected pixels (2x2 max.)
cd34021-a.fm 15/01/98 9 VV6300 sensor system clock generation VV6300 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the clki and clko pins. the device can also be driven directly from an external clock source driving clki. camera clock source for greater flexibility the input frequency can be divided by 1, 2, 4 or 8 to select the pixel clock frequency. two bits in the clock division register in the serial interface select the input clock frequency divisor. the table below gives the different frame rates that can be selected, when clki = 14.318mhz, for each divisor. the default clock divisor setting is a divide by 2. to achieve maximum frame rates data is converted at 4 bit resolution. clki (mhz) divisor pixel freq. (khz) frame rate 1 (fps) 1. approximate frame rate. assumes 160 x 120 image format, parallel data output and 4 bit data conversion comments 14.318 0 0 1 1790 59.98 default 14.318 0 1 2 895 29.99 14.318 1 0 4 448 15.01 14.318 1 1 8 224 7.5 clock division (60hz video mode) x1 c2 c1 r1 32 31 ckin ckout clk VV6300 32 31 ckin ckout VV6300 cmos driver clock source r2 c1=c2=47pf r1=1m w r2=510 w x1= 14.318mhz (up to 60fps) 17.73mhz (up to 50fps) clock division clk clock division
cd34021-a.fm 15/01/98 10 VV6300 sensor image format VV6300 has a single output image size, 160 x 120 pixel. the image size can be modified by asserting the enable borders serial interface register bit, (setup1, [001_0001 2 ]). the extended image size is 164 x 124 pixels. the default image format is 160 pixels by 120 lines. image format selection the diagram below shows the relationship between the default 160 x 120 pixel image and the extended 164 x 124 pixel format. a border, 2 pixels wide is enabled around the basic array. output image dimensions enable borders image size (column x row) comment 0 160 x 120 default 1 164 x 124 164 124 160 120
cd34021-a.fm 15/01/98 11 VV6300 sensor frame timing the VV6300 frame rate depends upon: (i) the frequency of the system clock (clki) (ii) the adc conversion accuracy (8-bit or 4-bit) (iii) the internal clock divisor selected (1, 2, 4, or 8) (iv) the output format selected (8-wire, 4-wire, serial or uart) user can set their own values for clki, the adc conversion rate and also the clock divisor setting, subject to achieving a frame rate up to 60 frames/sec. the frame rate is determined in the following way: an example is given with a clock input of 14.318mhz, 160 x120 image format, 8-bit adc conversion rate and a clock divisor of 2. 1. determine clock input (clki) frequency - 14.318mhz 2. pixel period = (divisor x conversion factor x output format factor) / clki clock divisor = 1, 2, 4 or 8. conversion factor = 8 for 8-bit adc accuracy = 4 for 4-bit adc accuracy output format factor = 2 for 8-wire, 4-wire, serial output modes = 6 for uart mode example: pixel period = (2 x 8 x 2) / 14.318mhz = 2.235 m s 3. line period = (no. of visible pixels + line overhead) x pixel period the number of visible pixels per line is 160. the interline pixel period overhead (including the 4 border pixels that can be enabled to qualify extra video information) is mode dependent, 43 pixel periods for 60hz mode or 141 pixel periods for 50hz mode. example: line period = (160 + 43) x 2.235 m s= 453.705 m s 4. frame period = (no. of visible lines + frame overhead) x line period for the purposes of calculating the effective frame rate the number of active lines is assumed to be fixed at 120. the frame overhead (which includes the 4 border lines that can be enabled to qualify extra video information) has a constant value of 27 line periods. example: frame period = (120 + 27) x 453.705 m s= 66.694ms frame rate = 1 / frame period = 15 frames per second
cd34021-a.fm 15/01/98 12 VV6300 sensor digital data output modes VV6300 provides several different output modes. the different data formats are selected via the appropriate register in the serial interface, setup0, [001_0000 2 ], bits 5 and 6. 8-bit or 4-bit pixel data conversion is also selected via the serial interface, setup1, [001_0001 2 ]. if 4-bit pixel data conversion is selected as well as 8- wire parallel output format then 2 consecutive pixel nibbles may be packed into a single output byte therefore increasing the effective frame rate. frame level formatting the frame level format for each mode is common and is given below. fst can be used for frame synchronisation. the fst pulse is exactly one line period in length and the rising edge occurs just before the status line start sequence (see line level formatting) is output. frame format (160 x 120 mode) frame format (164 x 124 mode) setup bit 6 setup bit 5 description comment 0 0 8-wire parallel 0 1 4-wire parallel default 10 serial 11 serial uart data output modes bl line fst bl st bk bk bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl fe bl st bl bl bl vl bl bl bl bl bl bl vl vl vl vl vl vl vl bl bl line fst black lines (bk) blank lines (bl) visible lines (vl) start / status line (st) 120 visible lines frame start bl frame end (fe) frame period = 147 lines vl bl line fst bl st bk bk bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl fe bl st bl bl bl vl vl vl bl bl bl vl vl vl vl vl vl vl vl bl bl line fst black lines (bk) blank lines (bl) visible lines (vl) start / status line (st) 124 visible lines frame start vl frame end (fe) frame period = 147 lines vl
cd34021-a.fm 15/01/98 13 VV6300 sensor line level formatting each line type (black, blank, visible) has a specific format associated with it independent of the data output format selected. each line begins with a start sequence of ff h ff h 00 h followed by xy h where xy h indicates the line type. the next two bytes provide supplementary data (specifically the line number within the current frame). following this data are two guaranteed blank bytes (07 h 07 h for 8 bit modes, 01 h 01 h for 4 bit modes). if the border lines/pixels have been enabled the next 2 bytes will be visible pixels otherwise they shall appear as blank bytes. the next part of the line is reserved for the 160 visible pixels. the 4 bytes following the visible pixels are formatted in the same way as the 4 bytes preceeding the 160 visible pixels. at the end of each line, an end of line sequence is produced, (ff h ff h 00 h 80 h ). if the line is within the visible part of the frame, (lines 11 to 134 if the border lines are enabled otherwise lines 13 to 132), the end of line sequence is immediately followed by 2 bytes containing the mean values for the central 128 pixels. the first byte contains the mean value for the first 64 pixels of the middle 128 pixels and the second byte contains the mean value for the latter 64 pixels of the middle 128 pixels. the 128 pixels comprise the standard 120 visible pixels, the 4 border pixels and an extra 4 border pixels that are never enabled as visible pixels but are used for exposure control and hence contribute to the mean pixel value for the line. if the line type is not visible then the two bytes following the end of line sequence will contain 07 h 07 h . for the remainder of the interline period the data output is always ff h . sensor status and configuration information is output during the frame start line, (line 0), each data byte is separated by a blank value (07 h ) to avoid possible false line start conditions being generated. the information output during the status line reflects, if the sensor is operating in 8bit adc mode, the first 64 locations in the serial interface register map. if the sensor is operating in 4 bit mode less data can be output during the status line. all the serial interface registers are 8bit values therefore 2, 4bit pixel periods are required to output a single serial interface location. note that the serial interface data is only output during the visible monochrome pixels of the status line. this allows for one quarter of the serial interface address space to be output during any status line. it is possible to select the remaining registers in the serial interface for output, (see serial interface register setup 2, bits 7:6). the end of frame line, it is actually 2 lines prior to the status line will output the 4 exposure control bin averages during the first 4, (or 8 if operating in 4bit modes) monochrome pixels. again the data is separated by mode dependent padding data.
cd34021-a.fm 15/01/98 14 VV6300 sensor line code nibble x h [1 c 2 c 1 c 0 ]nibble y h [p 3 p 2 p 1 p 0 ] end of line 1000 2 (8 h ) 0000 2 (0 h ) blank line (bl) 1001 2 (9 h ) 1101 2 (d h ) black line (bk) 1010 2 (a h ) 1011 2 (b h ) visible line (vl) 1011 2 (b h )0110 2 (6 h ) start of frame (sof) 1100 2 (c h ) 0111 2 (7 h ) end of frame (eof) 1101 2 (d h ) 1010 2 (a h ) reserved 1110 2 (e h ) 1100 2 (c h ) reserved 1111 2 (f h ) 0001 2 (1 h ) (i) line number (l 11 msb) odd word parity or (ii) if line code = end of line then mean pixel value for first half of the line mean pixel value for second half of the line l 7 l 8 l 6 p l 11 0 l 10 l 9 l 1 l 2 l 0 p l 5 0 l 4 l 3 m 2 m 3 m 1 m 0 m 6 m 7 m 5 m 4 (line code) escape/sync sequence f h f h f h f h 0 h 0 h y h x h d 2 d 3 d 0 d 1 p 2 p 3 p 1 p 0 nibble x h nibble y h c 2 1 c 1 c 0 command 4-wire output mode ff h ff h 00 h xy h d 3 d 2 d 1 d 0 8-wire output mode supplementary data nibble d 3 nibble d 2 nibble d 1 nibble d 0 n 2 n 3 n 1 n 0 n 6 n 7 n 5 n 4
cd34021-a.fm 15/01/98 15 VV6300 sensor line coding blank black frame visible ff h ff h c7 h ln 07 h 07 h ff h 00 h ff h 07 h 80 h 07 h 07 h sensor status data ff h ff h 00 h 07 h 07 h ln 07 h frame sd 07 h sd 07 h sd 07 h sd 07 h sd 07 h 00 h sd 07 h sd 07 h sd 07 h ff h ff h ff h ff h line start sequence line start line type line number ff h line end sequence line end next line start inter-line period ff h ff h ab h ln 07 h 07 h ff h 00 h ff h 07 h 80 h 07 h 07 h black level pixel values (nominally - 10 h ) ff h ff h 00 h ln 07 h pv pv pv pv pv pv pv pv pv pv 00 h pv pv pv pv pv pv ff h ff h ff h ff h line start sequence line start line type line number ff h line end sequence line end next line start inter-line period ff h ff h 9d h ln 07 h 07 h ff h 00 h ff h 07 h 80 h 07 h 07 h blank level ( 07 h ) ff h ff h 00 h 07 h 07 h 07 h 07 h ln 07 h 07 h 07 h 07 h 07 h 07 h 07 h 07 h 07 h 07 h 07 h 00 h 07 h 07 h 07 h 07 h 07 h 07 h ff h ff h ff h ff h line start sequence line start line type line number ff h line end sequence line end next line start inter-line period ff h ff h b6 h ln 07 h 07 h ff h 00 h ff h mn 80 h 07 h 07 h 160 visible pixels ff h ff h 00 h ln mn pv pv pv pv pv pv pv pv pv pv 00 h pv pv pv pv pv pv ff h ff h ff h ff h line start sequence line start line type line number ff h line end sequence line end next line start inter-line period black = 10 h - white = f0 h line mean values ff h ff h da h ln 07 h 07 h ff h 00 h ff h 07 h 80 h 07 h 07 h ff h ff h 00 h 07 h 07 h ln 07 h mn mn mn 07 h 07 h 00 h 07 h 07 h 07 h 07 h 07 h 07 h ff h ff h ff h ff h line start sequence line start line type line number ff h line end sequence line end next line start inter-line period frame mean values end start 07 h 07 h 07 h 07 h 07 h 07 h 07 h 07 h 07 h 07 h mn 07 h 07 h 07 h 07 h 07 h 07 h
cd34021-a.fm 15/01/98 16 VV6300 sensor 8-wire parallel mode 8-wire parallel mode is selected when the appropriate bits are set via the serial interface. when 8-bit conversion mode is selected the 8-bit pixel data is output on pins data[7:0]. the start of a frame is indicated by a pulse on fst. the data is valid on the falling edge of the pixel sample clock fast qck (qck f ) or on each edge of the slow qck (qck s ). 8-wire parallel mode (8-bit pixel data) when 4-bit conversion mode is selected the 4-bit pixel data is output two bytes at a time on the data[7:0] pins. the first pixel is mapped onto data[7:4] and the second pixel is output on data[3:0]. this effectively doubles the pixel rate (and halves the frame period). 8-wire parallel mode (4-bit pixel data) data[7:0] qck f ff h ff h b6 h ln 07 h 07 h ff h 00 h ff h mn 80 h 07 h 07 h ff h ff h 00 h ln mn 00 h p117 p118 p119 p120 ff h ff h ff h ff h ff h data[7:0] ff h line start line no. line type line end line mean qck s qck f qck s p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 07 h 07 h 07 h 07 h data[7:4] f h f h 6 h ln 1 h 0 h f h mn 8 h 1 h f h f h 0 h p1 p118 ln mn p3 p5 p7 p9 p11 p13 p15 p17 p19 p21 0 h p23 p110 p112 p114 p116 f h f h f h f h f h b h ln 1 h p0 ln p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 0 h p22 data[3:0] 0 h f h mn 0 h 1 h f h f h 0 h p119 mn p111 p113 p115 p117 f h f h f h data[7:4] data[3:0] p104 p106 p108 p105 p107 p109 f h f h line start line no. line type line end line mean qck f qck s qck f qck s p25 p24 p102 p103 1 h 1 h 1 h 1 h
cd34021-a.fm 15/01/98 17 VV6300 sensor 4-wire parallel mode 4-wire parallel mode is selected when the appropriate bits are set via the serial interface. when 8-bit data conversion mode is selected (conv8 = 1) the 8-bit pixel data is output on pins data[7:4] in two 4-bit nibbles. the start of a frame is indicated by a pulse on fst. a qck sample edge is generated for each nibble. 4-wire parallel mode (8-bit pixel data) when 4-bit data conversion mode is selected (conv8 = 0) the 4-bit pixel data is output on pins data[7:4]. 4-wire parallel mode (4-bit pixel data) data[7:4] f h f h f h 0 h b h 6 h f h 0 h 7 h f h f h f h ln ln 0 h mn ln ln 0 h 7 h 0 h 7 h f h p0 data[7:4] 0 h 7 h 0 h 8 h 0 h 0 h mn f h f h f h f h f h mn f h mn f h f h p119 p118 p116 p117 p115 f h f h f h 0 h b h 6 h ln ln 0 h ln ln f h f h line start line no. line type line end data[7:4] qck f qck s qck f qck s qck f qck s 0 h 7 h 7 h 0 h 0 h 7 h 7 h 0 h data[7:4] f h f h f h 0 h b h 6 h f h 1 h 1 h f h f h f h ln ln 0 h mn ln ln 1 h 1 h p0 p1 p2 p3 f h p4 data[7:4] 0 h 8 h 0 h 0 h mn f h f h f h f h f h f h f h f h f h f h f h f h f h 0 h b h 6 h ln ln 0 h ln ln f h f h line start line no. line type line end data[7:4] f h f h p119 p118 p117 p116 p115 p114 p113 qck s qck f qck s qck f qck s qck f 1 h 1 h 1 h 1 h
cd34021-a.fm 15/01/98 18 VV6300 sensor serial mode serial mode is selected when the appropriate bits are set via the serial interface. when 8-bit data conversion mode is selected the 8-bit pixel data is output on pin data[0] least significant bit first. serial mode (8-bit pixel data) when 4-bit data conversion mode is selected (conv8 = 0) the 4-bit pixel data is output on pin data[0] least significant bit first. serial mode (4-bit pixel data) 0123 4 7 6 data[0] pixel_0 pixel_1 pixel_2 5 0123 4 7 6 5 012 3 data[0] qck ff h ff h b6 h ln 07 h 07 h ff h 00 h ff h mn 80 h 07 h 07 h ff h ff h 00 h ln mn p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 00 h p10 p116 p117 p118 p119 ff h ff h ff h ff h ff h data[0] qck ff h line start line no. line type line end qck f qck s 07 h 07 h 07 h 07 h 0 3 2 data[0] pixel_0 pixel_1 pixel_2 1 0 3 2 1 pixel_3 pixel_4 03 2 1 03 2 1 02 1 3 f h f h f h 0 h b h 6 h ln ln 0 h ln ln 1 h 1 h p2 p3 f h p4 f h f h 1 h 1 h f h f h f h mn p119 0 h 8 h 0 h 0 h mn p117 p118 p116 p114 p115 p113 f h f h f h f h f h f h f h f h f h f h f h f h f h 0 h b h 6 h ln ln 0 h ln ln f h data[0] qck data[0] qck data[0] qck line start line no. line type line end qck f qck s p5 p6 p112 p111 1 h 1 h 1 h 1 h
cd34021-a.fm 15/01/98 19 VV6300 sensor serial uart mode serial uart mode is selected when the appropriate bits are set via the serial interface. when 8-bit data conversion mode is selected the 8-bit pixel data is output on pin data[0] least significant bit first. each pixel is preceded by a start bit and followed by an additional data bit and two stop bits. serial uart mode (8-bit pixel data) when 4-bit data conversion mode is selected the 4-bit pixel data is output two pixels at a time on pin data[0] least significant bit first. each pixel is preceded by a start bit and followed by an additional data bit and two stop bits. serial uart mode (4-bit pixel data) all the above output format modes assume that the sensor is operating in the default sensor read-out mode, namely, non shuffle and a monochrome image size of 160 by 120. the visible image can be increased to 164 by 124. this image size will normally be selected when operating in colour modes. the extra border of pixels is required by color processor algorithms to help with interpolation at the edge of the pixel array. the pixel 0123 4 7 6 data[0] pixel_0 pixel_1 5 0 1 4 3 2 567 start bit least significant bit first unused data bit two stop bits data[0] ff h ff h b6 h ln 07 h 07 h ff h 00 h ff h mn 80 h 07 h 07 h ff h ff h 00 h ln mn p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 00 h p10 p116 p117 p118 p119 ff h ff h ff h ff h ff h data[0] ff h line start line no. line type line end 07 h 07 h 07 h 07 h 0123 0 3 2 data[0] pixel_0 pixel_1 1 0 1 0 3 2 123 start bit least significant bit first unused data bit two stop bits pixel_2 pixel_3 f h f h f h 0 h 0 h 8 h ln ln 0 h ln ln 1 h 1 h 1 h p0 p1 f h p2 f h f h 1 h 1 h f h f h f h mn p119 0 h 0 h e h 0 h mn p117 p118 p116 p114 p115 p113 f h f h f h f h f h mn f h mn f h f h f h f h f h 0 h 0 h 8 h ln ln 0 h ln ln f h data[0] data[0] data[0] line start line no. line type line end p3 p4 p112 p111 1 h 1 h 1 h
cd34021-a.fm 15/01/98 20 VV6300 sensor read-out is shuffled to avoid crosstalk between the color channels. the read-out order is all the odd column pixels followed by all the even column pixels. note: if this document has not been reproduced on a color printer then the color assignments are as follows: left region (row numbering from 0 to 127) - red rows 0,2,4,6 etc. green rows 1,3,5,7 etc. right region (row numbering from 0 to 127) - green rows 0,2,4,6 etc. blue rows 1,3,5,7 etc. qualifying the output data data is output from VV6300 in a continuous stream. by utilising signals, like fst, and key events, like the start of a line or the end of line, the user can sample and display the image data. qck is used to sample the data, as described in the previous section. by default the falling edge of qck will sample the data, however it is possible to use both the rising and falling edges of a slow qck qck s to sample the data. different sections of the frame can be enabled by qck. the options, which are selected via setup register4 in the serial interface, are as follows, firstly the qck can be disabled, therefore no data will be qualified. this is the default option. the second option is to have the qck free running where all the data is qualified. 128 21..147 168 qualified pixels 20..146 . . . . . . . . . bin1 - red note bin2 - green note bin3 - green note bin4 - blue note . . . . . . . . . . 1,3,5..167 0,2,4..166 column number shuffled pixel readout blue green green red even columns (0, 2, 4,...) odd columns (1, 3, 5,...) even rows (0, 2, 4,...) odd rows (1, 3, 5,...) bayer colourisation pattern.
cd34021-a.fm 15/01/98 21 VV6300 sensor the third option is to only qualify the image data, which also includes the 2 black calibration monitor lines, lines 1 and 2 in the frame. this option is further complicated in that extra black lines and the extra border pixels/lines can be enabled giving the following 4 options: 1. black lines (1-2) plus image (160 pixels by 120 lines) 2. black lines (1-8) plus image (160 pixels by 120 lines) 3. black lines (1-2) plus image (164 pixels by 124 lines) 4. black lines (1-8) plus image (164 pixels by 124 lines) the final option is to qualify the embedded frame control sequences as well as the image data. these control sequences are the 6 bytes at the start and at the end of each image line, where an image line is defined above. the frame start or status line, image and control sequence pixels, will also be qualified during this mode. qck exceptions the output data from VV6300 can be formatted in many ways, as detailed in an earlier section of this document. under certain operating conditions the relationship between qck and the output data is compromised. it is vital that the phase relationship between the output data stream and the qck must be maintained from line to line, for example ensuring that, if enabled, the line code byte is always qualified by the same edge of the qck, clearly only applicable when considering slow qck qualification. it is known that there are an odd number of pixel periods in each line of the frame. if the slow qck is selected then clearly two pixels are qualified during each qck cycle resulting in the following modes of operation requiring special care: 4 bit adc 8 wire output, 8 bit adc 8 wire output and 4 bit adc 4 wire output. during the interline period, when the data bus is outputting data fixed at ff (8bit adc) or f (4bit adc), the phase of the qck is toggled, this will occur during every interline period. for the 8bit 8wire or 4bit 4 wire options this change is a simple inversion. the 4bit 8wire option is not quite as straightforward. during the interline period the qck signal is changed from its former state to 1 of 3 other states. in addition 2 out of the 4 possible states are video timing mode blue green green red blue green green red blue green green red blue green green red 1 3 2 0 3 2 1 0 VV6300 image format 160 pixels 120 pixels 124 pixels 164 pixels 0, 1, 2, 3,... ... 160, 161, 162, 163 0, 1, 2, 3,... ... 120, 121, 122, 123 border rows and columns pixel array blue green green red blue green green red blue green green red blue green green red 163 162 161 160 121 123 122 120
cd34021-a.fm 15/01/98 22 VV6300 sensor dependent. please note that the number of nibbles/bytes qualified by the clocks described above, during the free running qck mode, will differ from the expected value, as follows: qck exception details serial interface - exposure control handshake the process of writing timed exposure, clock division or gain settings to VV6300 using the serial interface requires special attention. these timed parameters can be written to the serial interface at any point within the frame timing but will only be transferred from shadow registers to their active registers at a specific point within the frame timing, see diagram below. please note that writing immediate clock division or gain parameters are treated as a normal serial interface write messages. since the new external exposure, clock division or gain settings are written to shadow registers the user continues to have full read/write access to the serial interface. a handshake system has been implemented between the exposure controller and the serial interface to avoid the user writing, for example, a second external timed gain value while the exposure controller has yet to transfer the first external timed gain value from the shadow register to the active register. if an external timed gain message has been written a special flag will be raised to indicate that it has yet to be transferred to the active register. this flag is available to the user via reading the status 0 register in the serial interface. until the flag is lowered the user knows that it is not safe to write a further external gain value. identical handshake protocols are used to implement timed external exposure and clock division writes. operating mode number of pixels qualified 50 frames per second number of pixels qualified 60 frames per second qck f qck s qck f qck s 4bit 4wire 203 202 301 300 4bit 8wire 202 198 300 298 8bit 8wire 203 202 301 300 pixel qualification exceptions old_exp old_clock_div old_gain odd frame flag new_exp new_clock_div new_gain 1 frame period
cd34021-a.fm 15/01/98 23 VV6300 sensor auto black calibration black calibration is used to remove voltage offsets that cause shifts in the black level of the video signal. VV6300 is equipped with an automatic function that continually monitors the output black level and calibrates if it has moved out of range. black calibration can be split into two stages, monitor (1 cycle) and update (3 cycles). during the monitor phase the current black level is compared against two threshold values. if the current value falls outside the threshold window then an update cycle is triggered. the update cycle can also be triggered by a change in the gain applied to sensor core or via the serial interface. serial interface in order to be controlled and configured by its host, VV6300 can receive and transmit data via a two-wire serial interface. serial communication protocol the host must perform the role of a communications master and the camera acts as either a slave receiver or transmitter.the communication from host to camera takes the form of 8-bit data with a maximum serial clock frequency of up to 100khz. since the serial clock is generated by the host it determines the data transfer rate. the bus address for VV6300 is 20 h . data transfer protocol on the bus is shown below. data transfer protocol data format a message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start followed by another message. the first byte contains the device address byte which includes the data direction read/write bit. the device address is 32 10 write, 33 10 read . the 5 msbs of the address byte are fixed as 0010_0 2 . the lsb of the address byte indicates the direction of the message. an even address causes the addressed slave to receive information from the master (write), an odd address indicates message read by the master. data format after the read/write bit is sampled, the data direction cannot be changed, until the read/write bit next message is received. the next byte contains the location of the first data byte (also referred to as the index ).there may be up to 128 such locations. if the msb of the second byte is set the automatic increment feature of the address index is selected. 1 2 7891 2 3 - 8 9 start condition stop condition sda scl msb ack ack read/write bit acknowledge from receiver p s s address[7:1] r / w bit a data[7:0] a sensor acknowledges valid address acknowledge from slave index[6:0] inc p a a data[7:0] [0] 0 0 1 0 0 0 0
cd34021-a.fm 15/01/98 24 VV6300 sensor message interpretation all serial interface communications with the sensor must begin with a start condition. if the start condition is followed by a valid address byte then further communications can take place. the sensor will acknowledge the receipt of a valid address by driving sda low. the state of the read/write bit (lsb of the address byte) is stored and the next byte of data can be interpreted. during a write sequence the second byte received is an address index and is used to point to one of the internal registers. the msbit of the following byte is the index auto increment flag. if this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. the master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start , (sr) . if the auto increment feature is used the master does not have to send indexes to accompany the data bytes. as data is received by the slave it is written bit by bit to a serial/parallel register. after each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. during a read message, the current index is read out in the byte following the device address byte. the next byte read from the slave device are the contents of the register addressed by the current index. the contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. at the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. although VV6300 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor. at the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater the last location read from or written to. a subsequent read will use this index to begin retrieving data from the internal registers. a message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation. the programmers model there are 128, 8-bit registers within the camera, accessible by the user via the serial interface. they are grouped according to function with each group occupying a 16-byte page of the location address space. there are eight such groups, the primary categories are given below: ? setup registers with bit significant functions including status (read only) bits ? exposure parameters that influence output image brightness. ? system functions and test bit significant registers. any internal register that can be written to can also be read from.
cd34021-a.fm 15/01/98 25 VV6300 sensor a detailed description of each register follows. the address indexes are shown as binary in brackets. index name r/w default comments status 000_0000 ro 1100 0000 2 (c0 h ) reserved 000_0001 ro 0001 0010 2 (12 h ) 000_0010 status0 ro 0000 1000 2 (08 h ) system status information 000_0011 unused - 000_0100 line_count ro current line counter value 000_0101 leftav ro average value of pixels in the first half of the current line. 000_0110 rghtav ro average value of pixels in the second half of the current line. 000_0111 frame_av ro average value of pixels in a frame. 000_1000 bin1 ro partial frame average - bin1 000_1001 bin2 ro partial frame average - bin2 000_1010 bin3 ro partial frame average - bin3 000_1011 bin4 ro partial frame average - bin4 000_11xx unused - setup 001_0000 setup0 r/w 0010_0111 2 (27 h ) configure the digital logic 001_0001 setup1 r/w 0111_0000 2 (70 h ) configure the digital logic 001_0010 setup2 r/w 0001_1111 2 (1f h ) pixel counter reset value 001_0011 setup3 r/w 0000_1111 2 (0f h ) exposure control modes 001_0100 setup4 r/w 0000_0000 2 (00 h ) fst/qck options 001_0101 unused - 001_011x unused - 001_1xxx unused - exposure 010_0000 unused - 010_0001 fine r/w 0000_0000 2 (00 h ) fine exposure initially zero 010_0010 unused - 010_0011 coarse r/w 0111_0000 2 (70 h ) coarse exposure 010_0100 gain r/w 0000_0000 2 (00 h )gain value 010_0101 clk_div r/w 0000_0000 2 (00 h ) clock division 010_0110 gn_lim r/w 0000_0111 2 (07 h ) maximum allowable gain 010_0111 tl r/w 0101_0101 2 (55 h ) lower exposure control threshold. 010_1000 tc r/w 1001_0110 2 (64 h ) centre exposure control threshold. 010_1001 th r/w 0110_0110 2 (73 h ) upper exposure control threshold. 010_101x unused - 010_1xxx unused - system 111_0011 xfav r/w 1000_0000 2 (80 h ) external frame average 111_0101 dcth r/w 1000_0000 2 (80 h ) digital comparator threshold 111_1001 unused 111_1010 unused 111_1011 unused 111_11xx unused the programmers model
cd34021-a.fm 15/01/98 26 VV6300 sensor status 0 [000_0010 2 ] the loading of certain system parameters is timed to avoid disturbing the video signal part way through a frame. bits 0-2 can be polled to check that a value written to either the exposure, gain or clock division registers has been consumed or not. bit 3 is essentially an internal flag differentiating between consecutive frames. line_count [000_0100 2 ] the video timing logic is controlled by the pixel counter and the line counter. to reduce the level of digital switching noise these counters implement a gray count sequence, where only a single counter register can change state in a clock period. however the gray count sequence is user unfriendly,e.q. 248,232,233, 235,234. a binary version of the line count is generated internally, realising a 0,1,2,3,4..... sequence, and it is this count sequence that is read by the serial interface and hence made available to the sensor user. line_avg 0 [000_0101 2 ] & line_avg 1 [000_0110 2 ] the exposure controller accumulates the pixel output values. on a line by line basis the accumulation is performed in two stages. the qualified pixels in the left half of the video line are accumulated and then stored in a latch. the process is then repeated during the right half of the video line. during the interline line period (up until the latch that stores the value for the left half of the line is updated during the next line) the latches will present valid average 8-bit pixel values for both halves of the line. bit function default comment 0 exposure value update pending 0 new exposure setting sent but not yet con- sumed by the exposure controller 1 clock division value update pending 0 new clock division setting sent but not yet consumed by the exposure controller 2 gain value update pending 0 new gain value sent but not yet consumed by the exposure controller 3 odd/even frame 0 the flag will toggle state on alternate frames 4 black calibration fail flag 0 if the black calibration algorithm returns very poor black levels - outwith both the calibration and monitor windows then this flag will be set and it will stay set until the next successful cal- ibration is complete 7:5 unused 0 status 0 [000_0010 2 ] bits function default comment 7:0 line count 0000_0000 2 displays current line count line_count [000_0100 2 ] bits function default comment 7:0 line average 0 average pixel value for first half of current line. line_avg 0 [000_0101 2 ] bits function default comment 7:0 line average 0 average pixel value for second half of current line. line_avg 1 [000_0110 2 ]
cd34021-a.fm 15/01/98 27 VV6300 sensor frame_avg [000_0111 2 ] the average pixel values stored in latches halfway through and at the end of each active video line are ultimately stored in bins that will maintain a frame sum of the pixel values. at the end of the frame the values stored in these bins are used to determine the overall pixel average for the whole frame. bin1_avg [000_1000 2 ] bin2_avg [000_1001 2 ] bin3_avg [000_1010 2 ] bin4_avg [000_1011 2 ] bits function default comment 7:0 frame average 0 pixel average for previous frame frame_avg [000_0111 2 ] bits function default comment 7:0 bin1 average 0 pixel average for current line bin1_avg [000_1000 2 ] bits function default comment 7:0 bin2 average 0 pixel average for current line bin2_avg [000_1001 2 ] bits function default comment 7:0 bin3 average 0 pixel average for current line bin3_avg [000_1010 2 ] bits function default comment 7:0 bin4 average 0 pixel average for current line bin4_avg [000_1011 2 ]
cd34021-a.fm 15/01/98 28 VV6300 sensor setup 0 [001_0000 2 ] setup registers 0,1,2,3 and 4 are used to alter the operating parameters of the sensor. all of these registers can be written to and read from. setup 0 register controls some fundamental exposure and output format parameters. defaults are shown in bold. setup 1 [001_0001 2 ] setup 1 register controls registers that are less likely to be modified on a regular basis. the user should note that the border pixels/lines can be disabled/enabled independently from the enabling/disabling of the custom analogue horizontal shift register. bit function default comment 0 automatic exposure control. off/ on 1 enables or disables automatic exposure control. current exposure value is frozen when disabled. 1 clamp fine exposure off/ on 1 if this bit is set and aec is enabled and the coarse exposure has exceeded the clamp threshold, 16, then the fine exposure will be clamped to 0. 2 automatic gain control. off/ on 1 enables or disables automatic gain control. cur- rent gain value is frozen when disabled. 3 enable immediate gain update. off /on 0 allow manual change to gain to be applied imme- diately. 4 enable immediate clock divi- sion update. off /on 0 allow manual change to clock division to be applied immediately. 6:5 data format select. 01 00 - 8 wire parallel output 01 - 4 wire parallel output 10 - 2 wire serial output 11 - 1 wire serial output 7 3/4 crystal clock off /on 0 achieves clock division by 3 rather than 4. setup0 [001_0000 2 ] bit function default comment 0 enable additional black lines (3-8) off/ on 0 if enabled extra black lines are visible at device output 1 enable border pixels off /on 0 extends qualified image size to 164 x 124. default image size is 160 x 120 2 enable horizontal shuffle mode. off /on 0 the contents of the horizontal shift register are shuffled so that all the even columns then all the odd columns are read out. setup1 [001_0001 2 ]
cd34021-a.fm 15/01/98 29 VV6300 sensor setup 2 [001_0010 2 ] in many systems VV6300 will be continuously synchronised. during this synchronisation the video timing is reset to a fixed point within the frame timing. the counter reset value is definable. 3 enable sample mode off /on 0 if enabled the data bus will continuously out- put a 96 h pattern. with the sensor in this mode a user can determine the best point at which to sample the data. 4 status line data output enable. off/ on 1 enables the output of serial interface status information on the data bus. by default the bottom 64 locations from the serial interface will be output. 5 8-bit or 4-bit adc select 1 the analogue output adc can be configured to convert to 4-bit or 8-bit resolution. 6 50fps timing/ 60fps timing 1 the sensor will implement 60hz like line timing by default giving reduced flicker operation with 60hz source frequencies. if the supply frequency is 50hz then 50hz like timing should be selected. 7 external frame average off /on 0 normally the accumulator arithmetic logic calculates the frame average of the pixel samples. however if this bit is enabled then the user may specify a frame average. bit function default comment 5:0 pixel counter reset value. 011111 2 during synchronisation the pixel counter is reset to the defined value. 6 status information output option. off /on 0 selects which system parameters are output on status line. see table below. 7 status information output option. off /on 0 selects which system parameters are output on status line. see table below. setup 2 [001_0010 2 ] bit 7 bit 6 register address range 8-bit modes register address range 4-bit modes 00 00 h - 3f h 00 h - 1f h 01 40 h - 7f h 20 h - 3f h 10 - 40 h - 5f h bit function default comment setup1 [001_0001 2 ]
cd34021-a.fm 15/01/98 30 VV6300 sensor setup 3 [001_0011 2 ] 11 - 60 h - 7f h bit function default comment 3:0 exposure control mode select. 1111 2 the average value for the frame that the exposure controller uses can be calculated in a number of different ways. see table below. 4 autoload control 0 this bit controls the autoload feature . note1 6:5 exposure step size 01 selects exposure step size. 1/8 for fast but jerky convergence to 1/64 for slow but smooth convergence. default 1/16. 7 unused 0 setup 3 [001_0011 2 ] note1: the state of this pin can affect the autoload function in a number of ways. 1. if the autoload bit is high continuously and the autoload pin is also high then an autoload will not take place. 2. if the autoload bit is initially high and is then forced low then an autoload will take place regardless of the state of the autoload pin. 3. if the autoload pin is initially high and is then forced low an autoload will take place regardless of the state of the autoload bit. 4. a low to high transition on either the autoload bit or the autoload pin while VV6300 is running will have no effect on the autoload function. bit 3 bit 2 bit 1 bit 0 function 0000bin1 0001bin2 0010bin3 0011bin4 0100(bin1 + bin2) / 2 0101(bin3 + bin4) / 2 0110(bin1 + bin3) / 2 0111(bin2 + bin4) / 2 1000(bin1 + bin4) / 2 1001(bin2 + bin3) / 2 frame average options bit 7 bit 6 register address range 8-bit modes register address range 4-bit modes status line information options
cd34021-a.fm 15/01/98 31 VV6300 sensor setup 4 [001_0100 2 ] the data output on the serial wire or the 4 wire/8 wire busses can be qualified, if required, by an internally generated clock signal, qck. this clock can be configured variously. both a fast and a slow qck can be generated. if the former is selected then the falling edge of the clock will qualify the current data nibble/byte, i.e. if the sensor is operating in 4 bit-4 wire mode then any true 8 bit data (e.g. line type code) will be qualified on a nibble basis. if the slow qck option is preferred then both edges of this clock are used to qualify the current data nibble/byte. the qck function has a dedicated pin assigned, however by selecting the appropriate bits the fst pin can also output qck data. by default qck is disabled. however by writing the appropriate message, qck can be forced to free run, qualify the embedded coding sequences and the visible data or the visible data only. fst can also be enabled or disabled or alternatively the fst pin can output a timing signal to synchronise several VV6300 sensors or finally the fst pin can output the state of the custom analogue block successive approximation adc output comparator. 1010(bin1 + bin2 + bin3 + bin4) / 4 1011(bin1 + bin2 + bin3 + bin4) / 4 bit 6 bit 5 step size comment 00 1/8 0 1 1/16 default 1 0 1/32 1 1 1/64 exposure step size options bit function default mode 1:0 fst/qck pin mode. 00 2 fst pin qck pin 00 2 01 2 10 2 11 2 normal fst normal fst qck f inverted qck f qck s qck f qck s qck f 3:2 qck mode select 00 2 00 2 01 2 10 2 11 2 disable free running validate control and image data validate image data only 5:4 unused 00 2 7:6 fst mode select 00 2 00 2 01 2 10 2 11 2 disable fst enable fst synchronisation pulse output (sno) output adc comparator output, cpo setup 4 [001_0100 2 ] bit 3 bit 2 bit 1 bit 0 function frame average options
cd34021-a.fm 15/01/98 32 VV6300 sensor exposure control registers [010_0001 2 ] - [010_1001 2 ] there is a set of parameters that control the time that the sensor pixels are exposed. the parameters are as follows: fine and coarse exposure time, clock division control and finally gain control. the latter parameter does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core. an internal automatic algorithm will, if enabled, continually monitor the pixel output and then, if required, use this data to correct the current exposure. manually changing the divisor applied to the incoming crystal clock can alter the effective integration of the sensor. by slowing the internal clock down the integration period can be increased, i.e. halving the pixel clock frequency will double the integration period. if the user wishes to use the automatic exposure algorithm, the automatic exposure control (controlling fine and coarse exposure) must be enabled. additional gain control is optional. it is also possible to change the gain manually via the serial interface even if the exposure is adjusted automatically. if a user wishes to write an external value to one of the automatic exposure algorithm registers then it is advised that the automatic control for that register be disabled prior to using the serial interface to write the external value. note: the external exposure (coarse, fine or gain) values do not take effect immediately. data from the serial interface is read by the exposure algorithm at the start of a video frame. if the user reads an exposure value via the serial interface then the value reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all the data written to the sensor. between writing the exposure data and the point at which the data is consumed by the exposure algorithm, bit 0 of the status register is set. the gain value is updated a frame later than the coarse and fine exposure parameters. the gain is applied directly at the video output stage and does not require the long set up time of the coarse and fine exposure settings. the automatic exposure algorithm uses a set of exposure threshold settings. these thresholds may also be modified by the user to alter the algorithms performance. the exposure algorithm uses these thresholds in a histogram. the three thresholds divide the histogram into 4 regions, very overexposed, overexposed, underexposed and very underexposed. the pixel data received from the sensor core is compared against the thresholds to determine the accuracy of the current exposure setting. a series of flags are set to describe the outcome of the histogram comparison and the new exposure setting can then be derived. each exposure parameter is subject to a maximum setting. the fine exposure setting can be clamped to a fixed value regardless of the decision made by the automatic algorithm. the clamping will occur if the coarse exposure setting exceeds a predetermined value and the clamping has been enabled via the serial interface. bit function default comment 7:0 fine exposure value 0000_0000 2 (00 h ) maximum fine (50hz mode) = ff h maximum fine (60hz mode) = a8 h fine exposure value [010_0001 2 ] bit function default comment 7:0 coarse exposure value 0111_0000 2 (70 h ) maximum coarse (50hz and 60hz modes) 91 h coarse exposure value [010_0011 2 ]
cd34021-a.fm 15/01/98 33 VV6300 sensor all 8 binary codes can be written to the core via the serial interface. only the 4 thermometer codes 000,001,011 and 111 are selected by the automatic exposure algorithm. the 4 other codes are however still valid and will be evaluated as detailed in the table below. it is clear, from the non-linear relationship between the binary code and the actual gain applied at the analogue output stage, that care should be taken when using non thermometer code gain settings. if the user writes a gain code of 110 (real gain = 1.600) and then enables automatic gain control and the controller then decided to reduce the gain, the new gain value would be 011 (real gain = 4.000) i.e. the effective applied gain at the analogue output stage has actually been increased. bit function default comment 2:0 gain value 0 8 possible gain states can be written via the serial interface gain value [010_0100 2 ] gain binary code actual signal gain 000 1.000 001 2.000 010 1.333 011 4.000 100 1.143 101 2.667 110 1.600 111 8.000 system gain bit function default comment 1:0 clock divisor value 0 pixel clock = crystal clock ? 2 n+1 clock divisor value [010_0101 2 ] the undivided input crystal clock is used by the clock generator circuitry, elements of the serial interface and a small number of other registers in the design. the remaining digital logic and the analogue circuitry, use internally generated clocks, namely the pixel clock and the faster adc clocks. these clocks are all slower versions of the crystal clock. the adc clocks may be up to half the crystal frequency, but can be further divided by factors of 2, 4 or 8. the pixel clock is in turn slower than the adc clock. if the adc is operating in 4 bit mode then the pixel clock is 1/4 the frequency of the adc clock, otherwise the pixel clock will be 1/8 the frequency of the adc clock. bit function default comment 2:0 gain limit 7 gain limit[010_0110 2 ]
cd34021-a.fm 15/01/98 34 VV6300 sensor frame average [111_0011 2 ] the exposure controller normally compiles a frame average from the data received from the core. a complete frame period is required to produce a frame average. this is clearly unacceptable for simulation and test purposes. it is possible to manually force a frame average via the serial interface. this feature together with the ability to curtail the frame duration will allow the behaviour of the exposure controller to be examined in a realistic simulation period. this register is read/write compatible digital comparator threshold [111_0101 2 ] the adc output from the cab can be digitally compared against a digital threshold. this threshold is fully programmable via the serial interface register. if the current adc output is greater than or equal to the programmed threshold then the modified adc output will be forced to the full scale output. the full scale value is mode dependent:- 224 for 8 bit adc conversion or 14 for 4 bit conversion. if the current adc output is less than the threshold then the modified adc output will be forced to minimum video. the minimum video setting (the black level) is again mode dependent:- 16 for 8 bit adc conversion or 1 for 4 bit conversion. if this feature is not enabled, (tms[7] = 0), then the adc output will pass unaltered. as indicated above the adc can convert to either 4 bit or 8 bit accuracy. when operating in a 4-bit mode the threshold value should be packed to the 4 most significant bits of the register i.e. if the required threshold bit function default comment 7:0 exposure lower threshold 85 exposure lower threshold [010_0111 2 ] bit function default comment 7:0 exposure centre threshold 100 exposure centre threshold [010_1000 2 ] bit function default comment 7:0 exposure higher threshold 115 exposure higher threshold [010_1001 2 ] bit function default comment 7:0 frame average 0 allow a synthetic frame average to be written to and used by the exposure controller frame average [111_0011 2 ]
cd34021-a.fm 15/01/98 35 VV6300 sensor value is 10 then 160 should be written to the threshold register. bit function default comment [7:0] threshold for digital comparator 128 the default has been set at the mid- range video setting for 8 bit adc conversion. the user must repro- gram the register if the test is run when the adc is converting to 4 bit accuracy. digital comparator threshold [111_0101 2 ]
cd34021-a.fm 15/01/98 36 VV6300 sensor types of messages this section gives guidelines on the basic operations to read data from and write data to the serial interface. the serial interface supports variable length messages. a message may contain no data bytes, one data byte or many data bytes. this data can be written to or read from common or different locations within the sensor. the range of instructions available are detailed below. ? no data byte, only sets the index for a subsequent read message. ? single location multiple data write or read for monitoring for real time control ? multiple location, multiple data read or write for fast information transfers. examples of these operations are given below. a full description of the internal registers is given in the previous section for all examples the slave address used is 0010000 2 =32 10 for writing and 0010001 2 =33 10 for reading. this corresponds to applying logical zero to both the sab0 and sab1 inputs. single location, single data write. when a random value is written to the sensor, the message will look like this: in this example, the coarse (index = 0100000 2 =32 10 ) exposure value has been written as 01010101 2 . the r/ w bit is set to zero for writing and the inc bit is set to zero to disable automatic increment of the index after writing the value. the location is preserved and may be used by a subsequent read. single location, single data read. a read message always contains the index used to get the first byte. this example shows a coarse (index = 32 10 ) value of 0101_0101 2 been read. note that the read message is terminated with a negative acknowledge (a ) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. this is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. 010_0000 0101_0101 sp aaa 00100000 0 sp aa a 00100001 010_0000 0101_0101 0
cd34021-a.fm 15/01/98 37 VV6300 sensor no data write followed by same location read. when a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. the read message then completes the message sequence. to avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages. in this example, the gain value (index = 36 10 ) is read as 15 10 : as mentioned in the previous example, the read message is terminated with a negative acknowledge (a ) from the master. same location multiple data write. it may be desirable to write a succession of data to a common location. this is useful when the status of a bit,(e.g. requesting a new black calibration), must be toggled. the message sequence indexes setup1 register and initially turns abc off. the next two data bytes then turn abc on and then finally off again, leaving it in the default state. same location multiple data read when an exposure related value ( coarse, fine , acc or gain ) is written, it takes effect on the output at the beginning of the next video frame, (remember that the application of the gain value is a frame later than the other exposure parameters). to signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written and is reset at the start of the next frame. this flag appears in status0 register and may be monitored by the bus master. to speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master acknowledges each byte read. in the next example, a fine exposure value of 0 is written, the status register is addressed (no data byte) and then constantly read until the master terminates the read message. s a sr a a a p 32 10 36 10 33 10 36 10 15 10 a 0 0 no data write read index and data s a 0 10 a a a 20 16 2 10 128 10 0 10 a 0 write setup1 turn off abc toggle force black cal.. p
cd34021-a.fm 15/01/98 38 VV6300 sensor multiple location write if the automatic increment bit is set, msb of the first data byte following the byte that contains the slave device address, then it is possible to write data bytes to many adjacent internal registers. a write to the black calibration parameters with their default values is shown in the following example. . multiple location read in the same manner, multiple locations can be read with a single read message. in this example the index is written first, to ensure the exposure related registers are addressed and then all seven are read note that a stop condition is not required after the negative acknowledge from the master. s a 0a a a 20 16 22 10 20 16 0 10 a 0 sr a a a a 21 16 0 10 1 1 1 a 0 sr write fine with zero address the status0 reg. a 1 0 a read continuously... ...until flag reset p s a 8 16 a a a 20 16 96 10 32 16 1 incremental write p incremental read s a a 32 10 32 10 1 sr 33 10 a a 32 10 1 coarse a a p fine gain gn_lim t1 tc a a a a no data write incremental read t2 a
cd34021-a.fm 15/01/98 39 VV6300 sensor serial interface autoload VV6300 can be configured automatically at power-up with any user defined set of system parameters using the serial interface auto-load feature. an external e 2 prom is used to store the configuration data. both shortly after power up and in response to an off-sensor soft reset on sin, the auto-loader will interrogate the e 2 prom to determine whether or not valid data is present. if no e 2 device is detected the auto-loader will shut-down and the serial interface register values will not be changed from their existing values. if, however, an e 2 device is detected, the auto-loader will begin to load data into the parameter registers from starting from location zero in the e 2 . the first byte is a register header code which determines the destination of the following data byte. this simple index & data format allows any sub-set of the VV6300 registers map to be configured at power-up and it allows them to be stored in the e 2 in any order. if the auto-loader detects the end-of-prom-contents code 00h followed by ffh, it will then issue a stop condition on the serial interface, raise a flag to indicate that the parameters have been loaded and close down. header rom contents xxh register ddh data xxh register ddh data 00h termination ffh example e 2 prom contents
cd34021-a.fm 15/01/98 40 VV6300 sensor serial interface timing serial interface timing characteristics serial interface timing characteristics parameter symbol min. max. unit scl clock frequency fscl 0 *** khz bus free time between a stop and a start tbuf *** - us hold time for a repeated start thd;sta *** - us low period of scl tlow *** - us high period of scl thigh *** - us set-up time for a repeated start tsu;sta *** - us data hold time thd;dat *** - us data set-up time tsu;dat *** - ns rise time of scl, sda tr - *** ns fall time of scl, sda tf - *** ns set-up time for a stop tsu;sto *** - us capacitive load of each bus line (scl, sda) cb - *** pf sda scl thd;sta tr thigh tf tsu;dat thd;dat tsu;sta tsu;sto ... ... thd;sta tlow tbuf stop start stop start all values referred to the minimum input level (high) = 3.5v, and maximum input level (low) = 1.5v
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cd34021-a.fm 15/01/98 42 VV6300 sensor example support circuit 0v c1 c2 c3 c4 ic1 32 31 2 47 9 28 46 45 15 19 (48 pin lcc) 22 21 33 34 20 29 36 27 r1 1 c5 24 23 25 26 sda scl sda scl d[7] vrt vcds hpix vbltw dvdd vcm/vref2v5 vbg qck fst sin vss1 vss2 vdd2 vdd1 4 17 16 clki clko c11 c8 c12 avcc 30 c7 vin gnd +8 to +12v dc c9 r2 VV6300 r4 d[6] d[5] d[4] d[3] d[2] d[1] d[0] autoloadb 38 ce 37 sin ce fst qck d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] hpix test 3 test dvss a0 vcc test scl a1 a2 sda gnd e 2 prom 6 5 8 7 3 4 1 2 ic3 c16 r5 r6 optional e 2 for configuration autoload agnd vss3 6 35 vdd3 14 13 c6 r3 r7 r8 c17 c16 44 vbloom c10 40 vreg c17 ic2 c13 vdd c18 c14 c15 5v r9 r10 5v
cd34021-a.fm 15/01/98 43 VV6300 sensor component part no. / provisional value rating / notes ic1 VV6300 vision camera chip (48 pin lcc) ic2 7805 5v regulator ic3 24c01 e2prom soic (8 pin) c3 10.0 m f c1,c2, c4-c11 0.1 m f c12, c13 4.7 m f c14, c15 100pf c16, c17 22pf c18 1nf r1 0 w r2 0 w r3 0 w r4 33 w r5, r6 2k2 w r7 1m w r8 10 w r9 1k8 r10 4k7
cd34021-a.fm 15/01/98 44 VV6300 sensor vlsi vision limited vlsi vision ltd. reserves the right to make changes to its products and spec- ifications at any time. information furnished by vision is believed to be accu- rate, but no responsibility is assumed by vision for the use of said informa- tion, nor any infringements of patents or of any other third party rights which may result from said use. no license is granted by implication or otherwise under any patent or patent rights of any vision group company. ? copyright 1996, vlsi vision vlsi vision agent or distributor uk headquarters aviation house, 31 pinkhill, edinburgh eh12 7bf scotland tel:+44 (0) 131 539 7111 fax:+44 (0)131 539 7141 email: info@vvl.co.uk usa western office 1190 saratoga ave., suite 180, san jose ca 95129 usa tel: +1 408 556 1550 fax: +1 408 556 1564 email: info@vvl.co.uk usa eastern office 571 west lake avenue, suite 12, bay head nj 08742 usa tel: +1 732 701 1101 fax: +1 732 701 1102 email: info@vvl.co.uk

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